This listing was posted on ITJobsWeb.
Design Technology Enablement Engineer
Location:
Hillsboro, OR
Description:
Job Description About DE organization: This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. About the role: As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools. Responsibilities: Define technical specification for Intel advance technology features to enable Intel-specific and industry standard EDA design tools. Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders. Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification. Joint effort with partners in DE organization to evaluate and isolate performance contributors for technology features as part of enablement. Build and qualify Process Pathfinding Kits and tools with quick turnaround time. Drive innovation and initiatives to enhance existing automation, tools, and methodology. Identify and analyze problems, plans, tasks, and solutions. Cultivate and reinforce appropriate group values, norms, and behaviors. Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications:BS in EE/CE with 5+ relevant industry experience OR MS in EE/CE with 3+ relevant industry experience OR Ph.D. in EE/CE with 1+ relevant industry experience in the following areas:- Experienced in Physical Verification tools like Calibre, ICV or Pegasus, with skill set and knowledge on LVS methodology.-Parasitic Extraction, Device Modeling and Simulation tools/flows-Custom design flow and related EDA tools-CMOS device physics, process technology and design rulesTools, flows, and methodology for optimal Product Performance/Power/Area/Cost (PPA)-One of the following: Python, PERL, TCLPreferred Qualifications:Familiar with Reliability verification, ESD concepts, Standard Cell Library and Memory Architectures#DesignEnablement Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Other Locations US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0263793pca3lyuhf
Company:
Intel
Posted:
May 12 on ITJobsWeb
Visit Our Partner Website
This listing was posted on another website. Click here to open: Go to ITJobsWeb
Important Safety Tips
- Always meet the employer in person.
- Avoid sharing sensitive personal and financial information.
- Avoid employment offers that require a deposit or investment.
To learn more, visit the Safety Center or click here to report this listing.
More About this Listing: Design Technology Enablement Engineer
Design Technology Enablement Engineer is a Engineering Engineer Job at Intel located in Hillsboro OR. Find other listings like Design Technology Enablement Engineer by searching Oodle for Engineering Engineer Jobs.
Design Technology Enablement Engineer is a Engineering Engineer Job at Intel located in Hillsboro OR. Find other listings like Design Technology Enablement Engineer by searching Oodle for Engineering Engineer Jobs.